Power FETs are well known in the art. A low on-resistance of the load path between source and drain is one of the most important variables of such devices. To achieve a low resistance, such devices are often designed as vertical transistors wherein the source of the FET is implemented and can be contacted by a metal layer on the top surface of the device and the backside comprises a metal layer that connects to the drain of the FET.
It is desirable to provide for a FET device that only provides for frontside contacts of the FET product.